The present invention relates to a semiconductor device, and more particularly to a package structure that may be applied to a chip size package (hereafter called xe2x80x9cCSPxe2x80x9d), fine pitch ball grid array (hereafter called xe2x80x9cFBGAxe2x80x9d), and so forth.
A ball grid array (BGA) package and a land grid array (LGA) have been known as the package structure of a semiconductor device. For a semiconductor with this structure, the chip carrier, which contains a semiconductor, has external electrode pads arranged on a grid on one side of the package. As compared with a quad flat package (QFP), this semiconductor device is greatly reduced in size because it has the external electrode pads on one side of the package. In addition, the pin-to-pin pitch, 1.5 mm or 1.27 mm, is relatively large as compared with that of a QFP which is 0.3 mm or 0.5 mm, making installation easier. Thanks to these advantages, BGA and LGA packages have been accepted as new semiconductor devices.
To make the package further smaller and to increase its density, a smaller BGA package was disclosed, for example, by Japanese Patent Kokai Publication No. JP-A-7-321157. This package comprises a semiconductor chip which has a plurality of connection pads on the surface; and a film carrier which has a wiring layer on the surface and a plurality of conductive bumps on the reverse side with the wiring layer and the bumps connected to the electrode pads via through-holes, in which a part of the wiring layer of the film carrier is connected to the pads on the semiconductor chip. In general, this type of package is substantially similar in size to the semiconductor chip which is mounted on the package, and the semiconductor device is built by mounting the semiconductor chip on the semiconductor package.
More specifically, an insulation film made of such materials as polyimide resin is attached with an adhesive on the surface, except on the electrode pads, of the semiconductor chip of a semiconductor device mounted on a semiconductor package. On the wiring on the insulation film are provided conductive bumps (hereafter called bumps) which are electrically connected to electrode pads on the semiconductor chip. The wiring on the insulation film is protected by a cover coat.
These bumps, arranged on a matrix on the insulation film, stick out of the cover coat.
The outer side of the insulation film on which the semiconductor is not attached and the part of the semiconductor chip on which the insulation film is not attached are sealed with mold resin.
A semiconductor device having this semiconductor package, which takes up space approximately equal to, or a little bit larger than, that of the semiconductor chip, may be mounted on a substrate such as a mother board, making it possible to mount many semiconductor devices in a limited space.
While the external electrode pads on the conventional BGA are arranged at a pitch of 1.27 mm-1.00 mm, the external electrode pads on the CSP or FBGA are arranged at a pitch of 0.8 mm or less to ensure high-density packaging. FIG. 6 shows a cross sectional view of the conventional CSP mounted on a substrate. In FIG. 6, 1 refers to an insulation flexible film, 2 refers to a semiconductor chip, 3 refers to a mold resin, 4 refers to solder bumps and 6 refers to the substrate on which the semiconductor device is mounted. As shown in the figure, the electrode pads on the semiconductor chip 2 are connected directly to the conductive electrode bumps (not shown in the figure) on the reverse side of an insulation flexible film 1.
It is expected that a semiconductor device with a semiconductor package will have more pins as the semiconductor chip have more electrode pads. To cope with the increase in the number of electrode pads, it is necessary to increase the number of bumps, to reduce the pitch between each two bumps, and to reduce the size of the bump.
The reduction in the pad-to-pad pitch and in the bump size to accommodate more pins results in a weak connection between the bumps and the lands disclosed on the insulation film.
In addition, the reduction in the bump size reduces the clearance between the semiconductor device and the substrate, affecting reliability when the temperature changes after installation.
The semiconductor package with this structure, with a sealing resin not only on the top or bottom of the semiconductor chip but also on the sides, allows bumps to be provided on the pads directly below the semiconductor chip (hereafter called xe2x80x9cPan-inxe2x80x9d) as well as on the outer parts (hereafter called xe2x80x9cfan-outxe2x80x9d) of the semiconductor chip.
However, the analysis made by the inventor of this invention reveals that a change in the temperature caused by the heat generated within the semiconductor device causes a thermal stress in the semiconductor device and, in addition, warps the package resulting in a reduced reliability after mounting (see FIG. 7). Assume a mold resin 3 has a large coefficient of thermal expansion and the semiconductor chip 2 has a small coefficient of thermal expansion. Then, the package warps as shown in FIG. 7 (B) when the temperature is high, and as shown in FIG. 7 (C) when the temperature is low because the resin side shrinks, based on the difference in the coefficient of thermal expansion.
According to a primary object of the present invention seeks to solve the problems associated with a thermal stress generated in the semiconductor device and a warp in the package caused by the thermal stress.
It is a concrete object of this invention is to provide a semiconductor device which reduces a thermal stress and therefore reduces or eliminates a warp in the semiconductor device and which ensures connection reliability of the semiconductor device.
Further objects of the present invention will become apparent in the entire disclosure.
To achieve the above objects, a semiconductor device according to a first aspect of the present invention provides a semiconductor device in which an insulation flexible film is laminated to a semiconductor chip, the insulation flexible film having on an obverse side thereof a plurality of electrode pads and having on a reverse side thereof a plurality of electrodes electrically connected to the plurality of electrode pads, the semiconductor chip being sealed on the chip-mounting side of the insulation flexible film with a resin, wherein the resin has a thickness on the semiconductor chip equal to or less than the thickness of the semiconductor chip.
According to a second aspect of the present invention there is provided a semiconductor device in which an insulation flexible film is laminated to a semiconductor chip, the insulation flexible film having on an obverse side thereof a plurality of electrode pads and having on a reverse side thereof a plurality of electrodes electrically connected to the plurality of electrode pads, the semiconductor chip being sealed on the chip-mounting side of the insulation flexible film with a resin, wherein the thickness of the resin sealing the sides of the semiconductor chip is equal to or less than the thickness of the semiconductor chip.
According to a third aspect of the present invention there is provided a semiconductor device as defined by the first aspect wherein the thickness of the resin disposed on the top of the semiconductor chip is equal to or less than the thickness of the semiconductor chip and wherein the height of the resin sealing the sides of the semiconductor chip is lower than the height of the resin sealing the semiconductor chip.
According to a fourth aspect of the present invention there is provided a semiconductor device as defined by the first aspect wherein the thickness of the resin disposed at an outer portion of the resin sealing the sides of the semiconductor chip is less than the thickness of the resin at an inner portion immediately sealing the sides of the semiconductor device.
According to this invention the semiconductor device has a semiconductor chip stuck on an insulation film with a wiring layer, and the semiconductor chip is sealed on the chip-mounting side of the insulation film with a resin, wherein the thickness of the sealing resin on the top of the semiconductor chip is less than the thickness of the semiconductor chip.
This invention reduces a warping introduced by a difference between the coefficient of thermal expansion of the semiconductor chip and that of the sealing resin when the temperature changes. This, in turn, reduces stress generated in the electrical contacts provided between the semiconductor device and the substrate, thereby increasing the reliability of the semiconductor device package.
According to the third and fourth aspects even as warping is introduced by the difference in the coefficient of thermal expansion between the semiconductor chip and that of the sealing resin when the temperature changes, a stress transmitted to the electrical contacts other than those provided between the semiconductor chip and the substrate, is reduced thereby increasing the reliability of the semiconductor device package.